features meets requirements of telcordia gr-253-core for sonet internal clocks and gr-1244-core for stratum 3 clocks meets requirements of itu-t g.813 option 1 and option 2 for sdh equipment clocks (sec) provides oc-3/stm-1, ds3, e3, 19.44mhz, ds2, e1, t1, 8khz and st-bus clock outputs accepts two independent reference inputs selectable 1.544mhz, 2.048mhz, 19.44mhz or 8khz input reference frequencies holdover accuracy of 0.02 ppm intrinsic jitter under 200 picoseconds pk-pk unfiltered on the 19.44mhz and 155.52mhz clocks output clock phase can be trimmed to support master-slave arrangements hardware mode, or optional microport mode with 8 bit microprocessor port access 3.3v supply jtag boundary scan applications sonet/sdh add/drop multiplexers sonet/sdh uplinks integrated access devices atm edge switches description the MT90401 is a digital phase locked loop (dpll) that is designed to synchronize sdh (synchronous digital hierarchy) and sonet (synchronous optical network) networking equipment. the MT90401 is used to ensure that the timing of outgoing signals remains within the limits specified by telcordia, ansi and the itu during normal operation and in the presence of disturbances on the incoming synchronization signals. the MT90401 can operate in free-run, locked or holdover mode. the loop filter corner frequency can be selected to suit sonet applications or to suit sdh applications. the MT90401 uses an external 20mhz oscillator as its master clock and it does not require external loop filter components. in hardware mode, the MT90401 can be controlled and monitored via external pins. in microport mode, a microprocessor can be used for more comprehensive control and monitoring. pb5429 issue 4 january 2001 ordering information MT90401ab 80 pin lqfp -40 to +85 c figure 1 - functional block diagram virtual reference selected refer- ence ieee 1149.1a reference select feedback tie corrector enable control state machine dpll state select state select frequency select mux input impairment monitor output interface circuit reference select mux tie corrector circuit ms1 ms2 fs1 fs2 tck sec rst rsel vdd vss tclr c1.5o c19o c2o c4o c8o c16o c44/c34 f0o f8o tdo tdi tms trst c6o holdover flock lock reference monitor prioor secoor d0/d7 a0/a6 cs, ds, r/w c155p/n c20i f16o master clock pcci pri MT90401 sonet/sdh system synchronizer product brief
MT90401 product brief 2 figure 2 - pin connections 80 pin lqfp for MT90401 pin description pin # name description 1ic internal connection . leave unconnected. 2-5 a1 - a4 address 1 to 4 (5v tolerant inputs). address and control inputs for the non-multiplexed parallel processor interface. 6v ss9 digital ground. 0 volts 7, 8 a5, a6 address 5, address 6 (5v tolerant input). address and control input for the non- multiplexed parallel processor interface. 9 sonet/ sdh sonet/ sdh (input). in hardware mode set this pin high to have a loop ?ter corner frequency of 70 millihertz and limit the phase slope to 885 ns per second. set this pin low to have a corner frequency of approximately 1.1 hertz and limit the phase slope to 50 ns per 125 microseconds. this pin performs no function if the device is not in hardware mode. 10 v dd1 positive power supply. digital supply (+3.3v + 5%). 11 v ss1 digital ground. 0 volts 12 f16o frame pulse st-bus 8.192 mb/s (cmos output). this is an 8khz 61ns active low framing pulse, which marks the beginning of an st-bus frame. this is typically used for st- bus operation at 8.192 mb/s. 13 c16o clock 16.384mhz (cmos output). this output is used for st-bus operation with a 16.384mhz clock. MT90401ab 40 42 44 46 48 50 52 54 56 58 60 22 24 26 28 30 34 36 38 32 62 80 78 76 74 72 68 66 64 70 20 18 16 14 12 10 8 6 4 2 tdi tclk tms tdo ic vss4 pri sec e3/ ds3 e3ds3/ oc3 c155p c155n vdd vdd2pll vss3pll ic vss2 fs1 t rst fs2 ms1 a2 a1 c4o c8o c16o f16o vss1 vdd1 sonet/ sdh a5 f0o c2o ic a3 a4 ms2 vss9 a6 f8o secoor oe cs rst hw d1 d2 d3 vss8 ic d6 r/ w ic vdd5 d4 d5 d7 ic a0 c1.5o c19o rsel tclr vdd3 vss6 c20i c34/c44 vss7 vdd4 holdover pcci lock flock ds ic prioor vss5 ic c6o d0
MT90401 product brief 3 14 c8o clock 8.192mhz (cmos output). this output is used for st-bus operation at 8.192mb/s. 15 c4o clock 4.096mhz (cmos output). this output is used for st-bus operation at 2.048mb/s and 4.096mb/s. 16 c2o clock 2.048mhz (cmos output). this output is used for st-bus operation at 2.048mb/s. 17 f0o frame pulse st-bus 2.048mb/s (cmos output). this is an 8khz 244ns active low framing pulse, which marks the beginning of an st-bus frame. this is typically used for st- bus operation at 2.048mb/s and 4.096mb/s. 18 ms1 mode/control select 1 (input). the logic level at this input is gated in by the rising edge of f8o. see pin description for ms2. this pin performs no function if the device is not in hardware mode. 19 ms2 mode/control select 2 (input). this input determines the state (normal, holdover or freerun) of operation. the logic level at this input is gated in by the rising edge of f8o. this pin performs no function if the device is not in hardware mode. 20 f8o frame pulse generic (cmos output). this is an 8khz 122ns active high framing pulse, which marks the beginning of a tdm frame. this is typically used for tdm streams operating at 8.192 mb/s. 21 e3ds3/ oc3 e3ds3 or oc-3 selection (input). in hardware mode a low on this pin enables the differential 155.52mhz output clock on the c155n/c155p pins; this will also cause the c34/ c44 pin to output its nominal clock frequency divided by 4. in hardware mode, a high on this pin disables the differential 155.52mhz output clock on the c155n/c155p pins; this will also cause the c34/c44 pin to output its nominal clock frequency. this pin performs no function if the device is not in hardware mode. 22 e3/ ds3 e3 or ds3 selection (input). in hardware mode a low on this pin selects a clock rate of 44.736mhz for the c34/c44 pin, while a high selects a clock rate of 34.368mhz. this pin performs no function if the device is not in hardware mode. 23 sec secondary reference (input). this is one of two (pri & sec) input reference sources (falling edge) used for synchronization. one of four possible frequencies (8khz, 1.544mhz, 2.048mhz or 19.44mhz) may be used. in hardware mode the selection of the input reference is based upon the ms1, ms2 and rsel control inputs. 24 pri primary reference (input). this is one of two (pri & sec) input reference sources (falling edge) used for synchronization. one of four possible frequencies (8khz, 1.544mhz, 2.048mhz or 19.44mhz) may be used. in hardware mode the selection of the input reference is based upon the ms1, ms2 and rsel control inputs. 25 v ss2 digital ground. 0 volts 26 ic internal connection. leave unconnected 27 v ss3 pll analog ground. 0 volts 28 v dd2 pll positive analog power supply. analog supply (+3.3v 5%). 29 vdd 3 positive power supply. digital supply (+3.3v 5%). 30 31 c155n, c155p lvds 155.52 mhz (output)). differential outputs generating a 155.52mhz clock 32 vss 4 digital ground. 0 volts 33 ic internal connection. leave unconnected 34 tdo ieee 1149.1a test data output (output). if not used, this pin should be left unconnected. pin description (continued) pin # name description
MT90401 product brief 4 35 tms ieee 1149.1a test mode selection (input) . if not used, this pin should be pulled high. 36 tclk ieee 1149.1a test clock signal (input) . if not used, this pin should be pulled high. 37 t rst ieee 1149.1a reset signal (input). if not used, this pin should be held low. 38 tdi ieee 1149.1a test data input (input). if not used, this pin should be pulled high. 39 fs2 frequency select 2 (input). this input, in conjunction with fs1, selects which of four possible frequencies (8khz, 1.544mhz, 2.048mhz or 19.44mhz) may be input to the pri and sec inputs. 40 fs1 frequency select 1 (input). this input, in conjunction with fs2, selects which of four possible frequencies (8khz, 1.544mhz, 2.048mhz or 19.44mhz) may be input to the pri and sec inputs. 41 prioor primary reference out of range (cmos output). a logic high at this pin indicates that the primary reference is off the pll center frequency by more than 12 ppm. the calibration is done on a 1 second basis using a signal derived from the 20mhz clock input on c20i. when the accuracy of the 20mhz clock is 4.6ppm the effective out of range limits of the prioor pin will be 16.6 ppm. 42 c1.5o clock 1.544mhz (cmos output). this output is used in t1 applications. 43 c6 clock 6.312mhz (cmos output). this output is used for ds2 or j2 applications. 44 ic internal connection. tie low for normal operation . 45 vss 5 digital ground. 0 volts 46 c19o clock 19.44mhz (cmos output). this output is used in ocn/sts-n and stm-n applications. 47 rsel reference source select (input). a logic low selects the pri (primary) reference source as the input reference signal and a logic high selects the sec (secondary) input. the logic level at this input is gated in by the rising edge of f8o. 48 tclr tie circuit clear (input). a logic low at this input clears the time interval error (tie) correction circuit resulting in a realignment of output phase with input phase. the tclr pin should be held low for a minimum of 300ns. when this pin is held low, the time interval error correction circuit is disabled. 49 vdd 3 positive power supply. digital supply (+3.3v 5%). 50 vss 6 digital ground. 0 volts. 51 c20i 20 mhz clock input (5v tolerant input). this pin is the input for the master 20mhz clock. 52 v ss7 digital ground. 0volts 53 c34/c44 controlled clock 34.368mhz / clock 44.736mhz (cmos output). this output clock is programmable to be either 34.368mhz (for e3 applications) or 44.736mhz (for ds3 applications). the output clock is controlled via control pins in hardware mode or control bits when the device is in microport mode. if the e3ds3/ oc3 control pin (in hardware mode) or if the e3ds3/ oc3 control bit (in microport mode) is high, the c34/c44 pin will output its nominal frequency. if the e3ds3/ oc3 control pin or control bit is low, the c34/c44 pin will output its nominal frequency divided by 4. (c8.5o/c11o) 54 v dd4 positive power supply. digital supply (+3.3v 5%). 55 holdover holdover (cmos output). this output goes high when the device is in holdover mode. pin description (continued) pin # name description
MT90401 product brief 5 56 pcci phase continuity control input (3v input). the signal at this pin affects the state changes between primary holdover mode and primary normal mode and primary holdover mode and secondary normal mode. the logic level at this input is gated by the rising edge of f8o. 57 lock lock indicator (cmos output). this output goes high when the pll is in frequency lock to the input reference. 58 flock fast lock mode (input). in hardware mode, hold this pin high to lock 8 times faster than normal to the input reference. this pin performs no function if the device is not in hardware mode. in fast lock mode, the wander generation of the pll is, of necessity, compromised. 59 ds data strobe (5v tolerant input) . this input is the active low data strobe of the motorola processor interface. 60 ic internal connection. tie low for normal operation. 61 secoor secondary reference out of capture range (cmos output). a logic high at this pin indicates that the secondary reference is off the pll center frequency by more than 12 ppm. the calibration is done o n a 1 second basis using a signal derived from the 20mhz clock input on the c20i pin. when the accuracy of the 20mhz clock is 4.6ppm the effective out of range limits of the secoor pin will be 1 6.6ppm. 62 oe output enable (input) . tie high for normal operation. tie low to force output clocks pins f16, c16, c8, c4, c2, f0 to a high impedance state. 63 cs chip select (5v tolerant input) . this active low input enables the non-multiplexed motorola parallel microprocessor interface of the MT90401. when cs is set to high, the microprocessor interface is idle and all bus i/o pins will be in a high impedance state. 64 rst reset (5v tolerant input). this active low input puts the MT90401 in a reset condition. rst should be set to high for normal operation. the MT90401 should be reset after power- up and after the selected reference frequency is changed. the rst pin must be held low for a minimum of 1 sec. to reset the device properly. 65 hw hardware mode (input) . if this pin is tied low, the device is in microport mode and is controlled via the microport. if it is tied high, the device is in hardware mode and is controlled via the control pins ms1, ms2, fs1, fs2, flock and sonet/ sdh. 66-69 d0 - d3 data 0 to data 3 (5v tolerant three-state i/o) . these signals combined with d0,d1 and d4-d7 form the bidirectional data bus of the parallel processor interface (d0 is the least signi?ant bit). 70 v ss8 digital ground. 0 volts. 71 ic internal connection. tie low for normal operation. 72 ic internal connection. tie low for normal operation. 73 v dd5 positive power supply. digital supply (+3.3v 5%). 74-77 d4 - d7 data 4 to data 7 (5v tolerant three-state i/o). these signals combined with d0-d3 form the bidirectional data bus of the parallel processor interface (d7 is the most signi?ant bit). 78 r/ w read/ write strobe (5v tolerant input). in motorola mode (r/ w), this input controls the direction of the data bus d[0:7] during a microprocessor access. when r/ w is high, the parallel processor is reading data from the MT90401. when low, the parallel processor is writing data to the MT90401. 79 a0 address 0 (5v tolerant input). address and control input for the non-multiplexed parallel processor interface. a0 is the least signi?ant input. 80 ic internal connection. tie low for normal operation. pin description (continued) pin # name description
MT90401 product brief 6 dim 80-pin 100-pin 128-pin 208-pin 256-pin min max min max min max min max min max a - 0.063 (1.60) - 0.063 (1.60) - 0.063 (1.60) - 0.063 (1.60) - 0.063 (1.60) a1 0.002 (0.05) 0.006 (0.15) 0.002 (0.05) 0.006 (0.15) 0.002 (0.05) 0.006 (0.15) 0.002 (0.05) 0.006 (0.15) 0.002 (0.05) 0.006 (0.15) a2 0.053 (1.35) 0.057 (1.45) 0.053 (1.35) 0.057 (1.45) 0.053 (1.35) 0.057 (1.45) 0.053 (1.35) 0.057 (1.45) 0.053 (1.35) 0.057 (1.45) b 0.009 (0.22) 0.015 (0.38) 0.007 (0.17) 0.011 (0.27) 0.001 (0.17) 0.011 (0.27) 0.001 (0.17) 0.011 (0.27) 0.005 (0.13) 0.009 (0.23) d 0.630 (16.00 bsc) 0.630 (16.00 bsc) 0.866 (22.00 bsc) 1.181 (30.00 bsc) 1.181 (30.00 bsc) d1 0.551 (14.00 bsc) 0.551 (14.00 bsc) 0.787 (20.00 bsc) 1.102 (28.00 bsc) 1.102 (28.00 bsc) e 0.025 (0.65 bsc) 0.020 (0.50 bsc) 0.020 (0.50 bsc) 0.020 (0.50 bsc) 0.016 (0.40 bsc) e 0.630 (16.00 bsc) 0.630 (16.00 bsc) 0.630 (16.00 bsc) 1.181 (30.00 bsc) 1.181 (30.0 bsc) e1 0.551 (14.00 bsc) 0.551 (14.00 bsc) 0.551 (14.00 bsc) 1.102 (28.00 bsc) 1.102 (28.00 bsc) d d1 e e1 a e a2 a1 notes: 1) not to scale 2) dimensions in inches 3) (dimensions in millimeters) 4) ref. jedec standard ms-026 b
MT90401 product brief 7 m mitel (design) and st-bus are registered trademarks of mitel corporation mitel semiconductor is an iso 9001 registered company copyright 2000 mitel corporation all rights reserved printed in canada technical documentation - not for resale world headquarters - canada tel: +1 (613) 592 2122 fax: +1 (613) 592 6909 north america asia/paci? europe, middle east, tel: +1 (770) 486 0194 tel: +65 333 6193 and africa (emea) fax: +1 (770) 631 8213 fax: +65 333 6192 tel: +44 (0) 1793 518528 fax: +44 (0) 1793 518581 http://www.mitelsemi.com information relating to products and services furnished herein by mitel corporation or its subsidiaries (collectively ?itel? is believed to be re liable. however, mitel assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, prod uct or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. neither the supply of such informa tion or purchase of product or service conveys any license, either express or implied, under patents or other intellectual property rights owned by mitel or licensed from third par ties by mitel, whatsoever. purchasers of products are also hereby notified that the use of product in certain ways or in combination with mitel, or non-mitel furnished goods or se rvices may infringe patents or other intellectual property rights owned by mitel. this publication is issued to provide information only and (unless agreed by mitel in writing) may not be used, applied or reproduced for any purpose no r form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. the products, their specifications, services and oth er information appearing in this publication are subject to change by mitel without notice. no warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. it is the user s responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. manufacturing does not necessarily include testing of all functions or parameters. these products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. all products and materials are sold and services pr ovided subject to mitel s conditions of sale which are available on request.
m mitel (design) and st-bus are registered trademarks of mitel corporation mitel semiconductor is an iso 9001 registered company copyright 1999 mitel corporation all rights reserved printed in canada technical documen t a tion - n o t for resale world headquarters - canada tel: +1 (613) 592 2122 fax: +1 (613) 592 6909 north america asia/paci?c europe, middle east, tel: +1 (770) 486 0194 tel: +65 333 6193 and africa (emea) fax: +1 (770) 631 8213 fax: +65 333 6192 tel: +44 (0) 1793 518528 fax: +44 (0) 1793 518581 http://www.mitelsemi.com information relating to products and services furnished herein by mitel corporation or its subsidiaries (collectively mitel) is believed to be reliable. however, mitel assumes no liability for errors that may appear in this publication, or for liability otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. neither the supply of such information or purchase of product or service conveys any license, either express or implied, under patents or other intellectual property rights owned by mitel or licensed from third parties by mitel, whatsoever. purchasers of products are also hereby noti?ed that the use of product in certain ways or in combination with mitel, or non-mitel furnished goods or services may infringe patents or other intellectual property rights owned by mitel. this publication is issued to provide information only and (unless agreed by mitel in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. the products, their speci?cations, services and other information appearing in this publication are subject to change by mitel without notice. no warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a speci?c piece of equipment. it is the users responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. manufacturing does not necessarily include testing of all functions or parameters. these products are not suitable for use in any medical products whose failure to perform may result in signi?cant injury or death to the user. all products and materials are sold and services provided subject to mitels conditions of sale which are available on request.
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